entity extensorSemSinal is
	port (
		entrada : in bit_vector (15 downto 0);
		saida : out bit_vector (31 downto 0)
	);
end extensorSemSinal;

architecture arc_extensorSemSinal of extensorSemSinal is

begin

	process (entrada)
	
		variable resultado : bit_vector (31 downto 0);
		
		begin
			resultado(15 downto 0) := entrada(15 downto 0);
			resultado(31 downto 16) := "0000000000000000";
			saida <= resultado;
	end process;
end arc_extensorSemSinal;